The present invention relates to the field of semiconductor manufacturing, and more particularly, to the formation of a silicon-on-insulator structure with improved capacitance characteristics.
Silicon-on-insulator (SOI) metal-oxide semiconductor field effect transistors (MOSFETs) are well known in the field of semiconductors. SOI MOSFETs have been demonstrated to be superior to bulk silicon MOSFETs in low-power, high-speed, very large scale integration (VLSI) applications. Some of the advantages include (1) less junction capacitance so that higher circuit speed can be achieved; (2) better device isolation; and (3) sufficient radiation hardness.
A conventional SOI structure comprises a substrate made of silicon, for example. An insulator layer is formed over the substrate, and is typically an oxide, such as silicon oxide. A silicon body, or silicon island, is formed on the insulator layer. This causes the insulator layer to be a xe2x80x9cburied oxidexe2x80x9d layer or BOX layer. The silicon bodies are isolated from one another by shallow trench isolation (STI) regions or other isolation regions. The source/drain regions are formed in the silicon body and the gate electrode is formed on top of the silicon body, thus forming the MOSFET device.
One of the limiting factors in transistor performance in SOI devices is the capacitance that exists from the source/drain regions to the substrate. The typical dielectric constant of the oxide that is conventionally used as the insulator layer of SOI devices is approximately 3.9. Reduction in the capacitance from the source/drain regions to the substrate will improve overall performance of the device by lowering the RC time constant.
There is a need for a SOI device that exhibits reduced capacitance between the source/drain regions and the substrate.
These and other needs are met by embodiments of the present invention which provide a semiconductor device comprising a substrate, dielectric support structures, and a silicon body held between the dielectric support structures and above the substrate such that a void is formed between the silicon body and the substrate.
The void between the silicon body and the substrate, as provided by the present invention, has the advantage of presenting a reduced dielectric constant and thereby reduction in the capacitance between source/drain regions and the substrate. For example, the dielectric constant of air is equal to one, which is significantly lower than the dielectric constant for silicon dioxide (approximately 3.9). The reduced capacitance improves the overall performance of the device of the present invention.
The earlier stated needs are also met by embodiments of the present invention which provide a method of forming a semiconductor device comprising the steps of forming a silicon-on-insulator precursor including a substrate, a buried oxide layer on the substrate, a silicon body on the buried oxide layer, and isolation regions surrounding the periphery of the silicon body. The portions of the buried oxide layer that are under the silicon body are etched to create a void between the substrate and the silicon body.
The etching of portions of the buried oxide layer in accordance with the embodiments of the present invention serves to create the void that provides the reduced dielectric constant between the source/drain regions and the substrate. The etching allows the creation of the void in a production-worthy method.
The earlier stated needs are also met by embodiments of the present invention which provide a method of forming a semiconductor device comprising the steps of forming a SOI structure having a substrate, an insulator on the substrate, a silicon body on the insulator, and isolation regions surrounding the periphery of the silicon body. In this method, a void is formed in the insulator layer between the silicon body and the substrate.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.